Facts

• Imports both SystemC and ANSI-C/C++ code
• Performs automatic power optimizing high level synthesis
• User controls power, area, and timing trade-offs
• Outputs RTL model, test bench, simulation scripts, and synthesis constraints
• Closes the gap between system and implementation models
• Outputs CPF/UPF power constraints
• Provides robust leakage modeling strategy
• Implements technology-driven modeling for temperature and voltage variations

• Energy saving up to 75%
• Up to 60x faster than lower-level methods
• Greatly reduces development cost for low power applications
• Quickly explore multiple architectures

• SystemC 2.1 and 2.2
• ANSI-C

• Power Optimized Verilog RTL code
• Verilog RTL testbenches and test vectors
• Micro Architecture Specification
• Power dissipation of system components
• Power dissipation and access statistics of memories
• Script files for interfacing to RTL logic synthesis tools
• CPF/UPF constraint formats