PowerOpt™
Power-Optimizing High Level Synthesis
ChipVision’s patented PowerOpt™ low-power system synthesis tool is the first design-for-low-power solution that lets designers synthesize power-efficient RTL architectures from the Electronic System Level (ESL), where the most significant power optimization can be achieved. Using PowerOpt, semiconductor developers accurately analyze power consumption at the system level using real activity data, and automatically achieve power savings of up to 75 percent compared to RTL designed by hand.
PowerOpt software automatically optimizes for low power while synthesizing ANSI C and SystemC code into Verilog RTL designs, producing the lowest-power RTL architecture. It optimizes algorithms, data path bit widths, resources, memory accesses, memory configurations, voltage and performance, clock gating and interconnects. The solution also implements leakage power optimizations. Sophisticated power analysis capabilities built into PowerOpt enable designers to interactively trade off power versus timing and area to make further optimizations to the design. Power constraints for downstream tools are output in Common Power Format (CPF) and Unified Power Format (UPF).
PowerOpt enables designers to explore the design space by interactively trading off between energy consumption, area, and performance (latency). PowerOpt stores each result so that the designer can compare different synthesized architectures to find the optimal power solution very early in the design flow.
PowerOpt generates RTL automatically, bridging the gap from specification to implementation. The designer is able to export the synthesis result at different levels of abstraction, either in functional or structural RTL. PowerOpt also produces an RTL testbench which is correlated to the ESL testbench and can be used to drive additional downstream RTL power optimization tools. In addition, PowerOpt generates a microarchitectural specification for the design.
PowerOpt is ideal for companies developing mobile communications, networking, consumer, or automotive applications, where extending battery life or reducing cooling requirements is important.
Pre-RTL energy savings:
PowerOpt enables trade-off analysis to create the lowest power implementations with up to 75% lower power consumption compared to traditional RTL flows.
Time to results:
Power optimization at the system level is much faster. PowerOpt enables multiple architectural explorations and produces significantly faster time to results compared to lower-level methods.
Code Compactness:
ESL code development is faster and far easier to maintain compared to the larger RT code base.